A conventional adder-subtracter assembly used for a digital computer typically operates sequentially in four steps: comparison of both the operands in magnitude and subtraction of exponents thereof; right-shifting one of the operands for a position alignment; adding-subtracting the fractions of both the operands; and shifting for a normalization of the result obtained by the addition-subtraction.
A conventional adder-subtracter assembly will be described with reference to the drawings. FIG. 1 shows a basic configuration of a conventional floating-point adder-subtracter assembly. In the same drawing, input operands 551 and 552 are compared to each other in their magnitude in a comparator and selector circuit 501, through which the fraction 554 of the smaller operand is supplied to a barrel right-shifter 503. The barrel right-shifter 503 functions for right-shifting the fraction 554 of the smaller operand for a position alignment of both the operands. The signal for the shift amount is supplied from an exponent subtracter 502 as a difference between the exponents of both the operands.
After the position alignment, the output of the barrel right-shifter 503 is added to or subtracted from the fraction 553 of the larger operand in an adder-subtracter 504, the output of which is then normalized in a normalization barrel shifter 505 for generating an output fraction expressed as 1.xxx . . . . In order to generate the normalization signal, a priority encoder 506 encodes the position of "1" appearing in the most significant bit of the output of the adder-subtracter 504. The normalization barrel shifter 505 operates for shifting in an amount corresponding to the output of the priority encoder 506.
The exponent is updated or adjusted in an exponent updater 507. The update of exponent is carried out by adding or subtracting the shift amount in the normalization shift to or from the exponent 555 of the larger operand supplied by the comparator and selector circuit 501. Both the outputs of the barrel shifter 505 and the exponent updater 507 as combined constitute the final output of the floating-point adder-subtracter assembly.
The floating-point adder-subtracter assembly as described above can be used also for an addition-subtraction of fixed-point operands. In this case, the adder-subtracter assembly is controlled in such a way that the adding or subtracting operation is carried out in the adder-subtracter 504 similarly to the addition-subtraction of the fraction as described above, and the remaining components or blocks in the adder-subtracter assembly function only for passing the data without any processing. The conventional adder-subtracter assembly is described in detail in "Computer Arithmetic PRINCIPLES, ARCHITECTURE, AND DESIGN" by Kai Hwang.
The conventional floating-point adder-subtracter assembly as described above has a drawback in which the addition-subtraction requires a large amount of time, since the operation includes in series among other procedures two barrel shifts, namely, a barrel right-shift for a position alignment and a barrel shift for a normalization, the barrel shifts each requiring a large amount of time.